The I2C standard (also referred to as I2C) was defined by NXP for a multi-master serial single-ended bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, cameras, or other electronic devices. The I2C bus includes a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for devices: master and slave. A master device is a node that generates the clock and initiates communication with slave devices. A slave device is a node that receives the clock and responds when addressed by the master device. The I2C bus is a multi-master bus which means any number of master devices can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). I2C defines basic types of messages, each of which begins with a START and ends with a STOP.
Various multi-protocol methods have been proposed to achieve higher bandwidth over an I2C-compatible bus while still permitting I2C legacy devices to remain operational over the I2C-compatible bus. For example, the I3C standard (defined by the MIPI Alliance) is an evolution of the I2C standard and provides backward compatibility for I2C devices. However, it is foreseen that even higher bandwidth may be desirable over the same bus in the future. Achieving such higher bandwidths over the bus may be hindered by the operation of legacy devices, such as I2C device and I3C devices.
Therefore, a solution is needed that allows selectively disabling legacy devices in a system in which a bus is shared by both legacy devices and next generation devices to permit higher bandwidths over the shared bus.